As integrated circuits have become more complex, the individual devices or integrated circuits, such as complementary metal oxide semiconductor (MOS) transistors, have become smaller and are more densely packed. Simply shrinking device dimensions is not sufficient to permit the increased complexity of the new circuits. New processing technologies and innovative devices are also required.
FIG. 1 shows a vertical structure of a prior art complementary MOS (CMOS) device having an n-channel and a p-channel MOS transistor. In FIG. 1, p-well region 40 and n-well region 50 are formed on a semiconductor substrate 10 to define p-channel and n-channel MOS transistors 20 and 30. Field oxide layer 60 is formed on the semiconductor substrate 10 to define active and inactive regions. Gate structures 70 and 80 are formed on the active regions of the p-channel and n-channel MOS transistors 20 and 30, respectively. Although the p-channel and n-channel devices 20 and 30, respectively, include a gate oxide layer, the gate oxide layer of gate structures 70 and 80 is not shown for reasons of clarity. Source and drain regions 90a and 100a of the n-channel MOS transistor are formed in the well region 40. Likewise, source and drain regions 90b and 100b of the p-channel MOS transistor are formed by injecting impurity ions in the well region 50.
In the prior art CMOS device structure, the channel length of each of the MOS transistors can be reduced. However, it is difficult to reduce the width of each of the source/drain regions because each of the source/drain regions are formed by impurity injection through windows. The source/drain regions of each transistor is formed by depositing a masking layer over the transistor, patterning the masking layer to form windows which expose portions of the source/drain regions, and then injecting impurity ions through the windows. A large width source/drain region results in increased junction capacitance which adversely affects the CMOS device's high speed operating characteristics.
If, however, the width of the source/drain region is shortened to improve the device's high-speed operating characteristics, it is difficult to sufficiently ensure large enough contact regions CNT for providing electrical contact between a source/drain electrode and the underlying source/drain region as shown in FIG. 2. All of the contact regions CNT are formed within the active region 55. The active region 55 is indicated by the dotted line shown in FIG. 2. Also, shown in FIG. 2 is the channel width Lg.
Moreover, after the formation of the gate electrode, a heat treatment process is performed on the device to activate impurity ions of the source/drain region preventing high-conductivity materials such as metal or the like used to form the gate electrode.
Accordingly, a need remains for a CMOS device and a method of fabricating CMOS device which reduces junction capacitance while improving high speed operating characteristics and ensuring adequate electrical contact between electrodes and the underlying source/drain regions.